1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using strain-inducing sources, such as an embedded strained layer in the drain and source regions to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
The fabrication of integrated circuits requires the formation of a large number of transistor elements on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the development of new, highly complex process techniques, for example, for compensating short channel effects, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling. Moreover, an increased carrier mobility may also compensate for other mechanisms required for reducing short channel effects, such as dopant increase in the channel region and the like.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility of electrons and holes, respectively. For example, for a typical transistor configuration, that is, a silicon crystal having a (100) surface orientation with the channel length aligned along the <110> orientation, uniaxial compressive strain along the channel length direction in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. On the other hand, the creation of tensile strain in the channel region of an N-channel transistor may increase electron mobility. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semi-conductor material, which may enable the fabrication of fast and powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Therefore, in some approaches, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create strain in the adjacent silicon channel region. To this end, respective sidewall spacers are formed at the gate electrode as required for the definition of the silicon/germanium regions, while the gate electrode is covered by a capping layer. Similarly, the NMOS transistors are completely covered by a capping layer. Then, the regions of the PMOS transistors exposed by the sidewall spacers are selectively recessed, while the gate electrode and the NMOS transistors are masked. Subsequently, a highly in situ doped silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth techniques. Since the natural lattice spacing of silicon/germanium is greater than that of silicon, the epitaxially grown silicon/germanium layer, adopting the lattice spacing of the silicon, is grown under compressive strain, which is efficiently transferred to the channel region, thereby compressively straining the silicon therein substantially along the channel length direction. This integration scenario results in a significant performance gain of the P-channel transistors.
Since the further device scaling may involve further performance reducing mechanisms for countering short channel effects, such as increased dopant levels in the channel region, high-k dielectrics in the gate insulation layer and the like, it is, however, of great importance to provide efficient techniques for compensating for or over-compensating for such mobility degrading approaches by efficiently increasing the charge carrier mobility for P-channel and N-channel transistors by more efficiently using and/or combining strain-inducing mechanisms, such as strained silicon/germanium material, strained silicon/carbon material and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.